The microprocessor industry is in the midst of a dramatic transformation. Up until recently, to boost microprocessor's performance it was solely relied on increasing clock frequency. Nowadays, however, the power consumption requirements coupled with the growing consumer demand, made the industry shift their focus from single-core to multi-core solutions, which offer an increase in performance without a proportional increase in power consumption. The embedded systems field is no exception, and the trend to use multi-core solutions has been rising substantially in the last few years.
Real-time systems have a need for deterministic behavior as well as rigorous temporal deadlines. With this in mind, operating systems suffer from the existence of a bifid priority space, dictated by the co-existence of synchronous threads managed by kernel scheduler and asynchronous interrupt handlers scheduled by hardware. This induces a well-identified problem termed rate-monotonic priority inversion. Regarding safety-critical real-time systems, where time and determinism play a critical role, the inherent possibility for delayed execution of real-time threads by hardware interrupts with semantically lower priority, can cause fatal consequences to human life.
Within this context, this dissertation presents the extension of a previous 'in-house' project, by proposing the implementation of a unified priority space approach Sloth in a multicore environment. To accomplish this it is proposed the offloading of the scheduling decisions and synchronization mechanisms to a Commercial Off-The-Shelf (COTS) hardware interrupt controller (removing the need for a software scheduler) on an ARM Cortex-A9 MPCore platform.