µRTZVisor is a microkernel-like architecture that is based on a refactoring of the RTZVisor - Real-Time TrustZone-assisted Hypervisor, which is a bare-metal embedded Hypervisor that relies on the TrustZone hardware architecture to provide the foundation to implement strong spatial and temporal isolation between multiple guest OSes, by virtualizing a physical core as two virtual cores, providing two execution environments: the secure and the non-secure worlds. Hypervisors can manage different instances of OSes and arbitrate their execution and resource usage, according to the chosen policy.
The use of Partial Reconfiguration (PR) allows the designer to define Partial Reconfigurable Regions (PRRs) in the Field Programmable Gate Array (FPGA) and reconfigure them during runtime. A Hypervisor that supports PR, brings benefits to the system. Aside from better FPGA resources usage, security can be expanded by implementing portions of hardware modules in different approaches for the same execution goal and alternate between them in runtime. Another improvement that it brings is in case of misbehaving critical hardware modules being detected, the hardware module can be replaced. PR in a Hypervisor also enables it to control and change hardware accelerators dynamically, which can be used to meet the guest OSes requests for hardware resources as the need appears.
Study different Partial Reconfiguration methods
Study of µRTZVisor and its architecture
Implement a set of hypervisor mechanisms to manage FPGA reconfigurable accelerators;
Extend uRTZVisor hypervisor to dynamically manage software and DPR hardware tasks;
Extend the uRTZVisor hypervisor security spectrum by implementing diversity through DPR;
Evaluation of the solution;
Writing and production of the dissertation.